Presented by Martin Langhammer, Sr. Principal Engineer, Intel. The dataflow flexibility of spatial architectures allows for the possibility of a higher “sustained to peak” TOPs/TFLOPs ratio. In this presentation we will describe the architecture of the Stratix 10 NX family, AI optimized FPGAs which contain a matrix of almost 4,000 AI tensor blocks, providing 130 TOPs/TFLOPs INT8/FP16 or 260 TOPs/TFLOPs INT4/FP12 peak performance. Large on board HBM stacks enable single node capability, and multiple banks of high-speed transceivers allow distributed or unrolled algorithms across the datacenter. The Linley Fall Processor Conference featured technical presentations addressing processors and IP cores for AI applications, embedded, data center, automotive, and communications. Session topic included AI in Edge Devices, Vector-Processing Cores, Advancing Cloud AI, The New Infrastructure Edge, Heterogenous Computing, SoC Design, In-Memory Compute, and Security. Proceedings from the event are available for download.